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graduate thesis
IMPLEMENTACIJA AES ALGORITMA OPTIMIZIRANA ZA FPGA
2024. urn:nbn:hr:228:292232
Gašperov, Duje
University of Split
University Department of Professional Studies
Department of Electrical Engineering

Cite this document

Gašperov, D. (2024). IMPLEMENTACIJA AES ALGORITMA OPTIMIZIRANA ZA FPGA (Graduate thesis). Split: University of Split. Retrieved from https://urn.nsk.hr/urn:nbn:hr:228:292232

Gašperov, Duje. "IMPLEMENTACIJA AES ALGORITMA OPTIMIZIRANA ZA FPGA." Graduate thesis, University of Split, 2024. https://urn.nsk.hr/urn:nbn:hr:228:292232

Gašperov, Duje. "IMPLEMENTACIJA AES ALGORITMA OPTIMIZIRANA ZA FPGA." Graduate thesis, University of Split, 2024. https://urn.nsk.hr/urn:nbn:hr:228:292232

Gašperov, D. (2024). 'IMPLEMENTACIJA AES ALGORITMA OPTIMIZIRANA ZA FPGA', Graduate thesis, University of Split, accessed 05 April 2025, https://urn.nsk.hr/urn:nbn:hr:228:292232

Gašperov D. IMPLEMENTACIJA AES ALGORITMA OPTIMIZIRANA ZA FPGA [Graduate thesis]. Split: University of Split; 2024 [cited 2025 April 05] Available at: https://urn.nsk.hr/urn:nbn:hr:228:292232

D. Gašperov, "IMPLEMENTACIJA AES ALGORITMA OPTIMIZIRANA ZA FPGA", Graduate thesis, University of Split, Split, 2024. Available at: https://urn.nsk.hr/urn:nbn:hr:228:292232

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Metadata
TitleIMPLEMENTACIJA AES ALGORITMA OPTIMIZIRANA ZA FPGA
Title (english)FPGA-OPTIMIZED AES ALGORITHM IMPLEMENTATION
AuthorDuje Gašperov
MentorTonko Kovačević (mentor)
Committee memberToni Jončić (član povjerenstva)
Committee memberMarko Vukšić (član povjerenstva)
GranterUniversity of Split
(University Department of Professional Studies)
(Department of Electrical Engineering)
Split
Defense date and country2024-09-18, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
Projektni zadatak bio je dizajnirati digitalni logički sklop s ciljem implementacije na FPGA platformi. Rješenje ću izraditi u Vivado razvojnom okruženju koristeći Verilog HDL za Xilinx Zynq Ultrascale+ MPSoC. Testiranje i implementaciju ću odraditi na Xilinx ZCU102 razvojnoj ploči.
Abstract (english)
The project task was to design a digital logic circuit with the aim of implementation on an FPGA platform. I will build the solution in Vivado development environment using Verilog HDL for Xilinx Zynq Ultrascale+ MPSoC. I will do the testing and implementation on a Xilinx ZCU102 development board.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:228:292232
Study programmeTitle: Electrical Engineering
Study programme type: professional
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike (magistar/magistra inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2024-11-05 14:39:52